Please enable JavaScript to view this site.

Application Gallery

Navigation: CMOS Image Sensors

Electrical Simulation Methodology

Scroll Prev Top Next More

The cost of CMOS image sensor pixel-based digital camera systems is being reduced through the use of smaller pixel sizes and larger fill-factors. However, CMOS pixel size reduction is only acceptable without sacrificing image quality. As CMOS pixel sizes continue to decrease, there is a reduction in image signal to noise as well as an increase in cross-talk between adjacent sensor pixels. These effects can be offset by careful design optimization through computer simulation which, at current pixel dimensions, requires a comprehensive solution involving both optical and electrical analysis.

 

In this topic we discuss the trends in CMOS image sensors, the implications for simulation, the types of results that can be simulated and describe the full simulation methodology to achieve them.

 

See also

CMOS image sensors

Related publications

F. Hirigoyen, A. Crocherie, J. M. Vaillant, and Y. Cazaux, “FDTD-based optical simulations methodology for CMOS image sensors pixels architecture and process optimization” Proc. SPIE 6816, 681609 (2008)

 

Wang, Xinyang, "Noise in Sub-Micron CMOS Image Sensors", Ph.D. Thesis, Delft University of Technology

cmos_screenshot

 

 

Copyright Lumerical Inc. | Privacy | Site Map